The present invention is related to digital-to-analog converter technology. More particularly, the present invention is related to a segmented digital-to-analog converter using a tri-level combination of unary and binary techniques such that differential non-linearity errors are minimized.
Digital-to-analog converters (DACs) may be arranged to convert digital code words into analog voltages. The digital code word consists of a number (N) of binary bits (b1 b2 . . . bN). The analog voltage from the DAC corresponds to a particular binary scaling of a full-scale voltage (VFS), where the binary scaling is related to the digital code word. The minimum step size for the analog output voltage, between adjacent code words, corresponds to VFS/2N. A typical conversion from the N-bit digital code word to an analog voltage (Vout) yields the following transfer function:   Vout  =      VFS    xc3x97          (                                    b            1                                2            1                          +                              b            2                                2            2                          +        …        +                              b            N                                2            N                              )      
The above identified equation results in a transfer function with equal step sizes between each adjacent code word. However, non-ideal conditions in the DAC implementation may have non-equal step sizes that result in errors in the conversion. A differential non-linearity (DNL) error in a DAC corresponds to a non-uniform deviation in the ideal step size between adjacent code words. Large differential non-linearity errors may result in an unchanged output voltage between adjacent codes such that the adjacent code is effectively missing.
Binary-weighted current steering DACs include an array of current sources that are arranged to provide a total current (Iout) to a load circuit in response to a digital code word. Each current source in the array is arranged to provide a portion of the total current (Iout) to the load circuit. The total current is given by the following transfer function:
Iout=b1xc3x97I+b2xc3x972*I+. . . +bNxc3x972Nxe2x88x921xc3x97I
The binary-weighted DAC is implemented with an array of unequal current sources that are scaled relative to one another to provide binary weighted currents. The worst code transitions are observed in the transfer function when a single larger current source is activated, and several smaller current sources are deactivated. Non-ideal output current can be observed at these code transitions due to mismatches between the current source elements, resulting in high DNL error. Mismatches in the relative accuracy of the current sources are primarily a result of processing variations. Binary DACs are very space efficient.
A unary DAC employs a thermometer decoder that is arranged to activate unit current sources, all of which have equal value, in sequence as the code word increases in value. For example, a 9-bit DAC has 512 steps from 0 to 511, where each step corresponds to an additional unit current source. As a code increases over the range of the transfer function, additional current sources are activated without deactivating any of the previously active current sources. The unary DAC results in excellent DNL error performance, at the cost of additional die area (or space).
Segmented DACs employ a combination of the binary weighted DAC and the unary DAC topologies. High-order bits are implemented in the unary portion, while low-order bits are implemented in a binary weighted portion. For example, a 9-bit DAC may be implemented as a segmented DAC with bits 1-5 being implemented in binary fashion, while bits 6-9 are implemented in unary fashion. For this example, the unary portion requires 16 unary current sources, while the binary weighted portion requires 5 binary current sources. The segmented DAC provides a good tradeoff between the unary and binary-weighted DAC implementations, with overall good DNL and reasonable space requirements (die area).
Briefly stated, a segmented digital-to-analog converter circuit that employs a tri-level technique that provides an output current in response to a conversion code that is provided by data bits. A decoder circuit is employed to provide control signals in response to the high-order bits, for the unary part. DAC slice circuits are selectively activated in unary fashion in response to a respective control signal. Each DAC slice circuit provides a binary weighted current to a summing node in response to the middle-order bits. One of the DAC slice circuits is selected to direct a portion of its total current to the input of a DAC_LOW circuit. The DAC_LOW circuit divides the input current using binary weighted current division and provides a divided current to the summing node in response to the low-order bits. At certain code transition, the previously selected DAC slice circuit directs its total current to the summing node, and another DAC slice circuit is selected to provide the input current to the DAC_LOW circuit. Since none of the currents from the DAC slice circuits are thrown away, differential non-linearity errors are minimized.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims.